cy2xl11 100 mhz lvds clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-42886 rev. *f revised march 18, 2011 features one low-voltage differential signaling (lvds) output pair output frequency: 100 mhz external crystal frequency: 25 mhz low rms phase jitter at 100 mhz, using 25 mhz crystal (637 khz to 10 mhz): 0.53 ps (typical) pb-free 8-pin tssop package supply voltage: 3.3 v or 2.5 v commercial temperature range functional description the cy2xl11 is a pll based high performance clock generator with a crystal oscillator interface and one lvds output pair. it is optimized to generate pci express, fc, and other high- performance clock frequencies. it also produces an output frequency that is four times the crystal frequency. it uses cypress?s low-noise vco technology to achieve less than 1 ps typical rms phase jitter, that meets high-performance systems? jitter requirements. output divider oe crystal oscillator clk# low-noise pll clk xout xin external crystal logic block diagram pinouts figure 1. pin diagram - 8-pin tssop 1 2 36 7 8 xout xin oe vss vdd clk# 45 vdd clk table 1. pin definition ? 8-pin tssop pin number pin name i/o type description 1, 8 vdd power 3.3 v or 2.5 v power supply. all supply current flows through pin 1 2 vss power ground 3, 4 xout, xin xtal output and inpu t parallel resonant crystal interface 5 oe cmos input output enable. when high, the output is enabled. when low, the output is high-impedance 6,7 clk#, clk lvds output differential clock output [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 2 of 9 frequency table input crystal frequency (mhz) pll multiplier value output frequency (mhz) 25 4 100 absolute maximum conditions parameter description condition min max unit v dd supply voltage ? ?0.5 4.4 v v in [1] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non operating ?65 150 c t j temperature, junction ? ? 135 c esd hbm esd protection (human body model) jedec std 22-a114-b 2000 ? v ul?94 flammability rating at 1/8 inch v?0 ja [2] thermal resistance, junction to ambient 0 m/s airflow 100 c/w 1 m/s airflow 91 2.5 m/s airflow 87 notes 1. the voltage on any input or io pin cannot exceed the power pin during power up. 2. simulated using apache sentinel ti software. the board is derived from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. no via s are included in the model. 3. outputs are terminated with 100 between clk and clk#. refer to figure 8 on page 5 . 4. i dd includes ~4 ma of current that is dissipated externally in the output termination resistor. 5. not 100% tested, guaranteed by design and characterization. 6. refer to figure 2 on page 4 . 7. refer to figure 3 on page 4 . operating conditions parameter description min max unit v dd 3.3 v supply voltage 3.135 3.465 v 2.5 v supply voltage 2.375 2.625 v t a ambient temperature ?5 70 c t pu power up time for all v dd to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms dc electrical characteristics parameter description test conditions min typ max unit i dd [4] power supply current with output terminated v dd = 3.465 v, oe = v dd , output terminated ? ? 120 ma v dd = 2.625 v, oe = v dd , output terminated ? ? 115 ma v od [6] lvds differential output voltage v dd = 3.3 v or 2.5 v, r term = 100 between clk and clk# 247 ? 454 mv v od [6] change in v od between comple- mentary output states v dd = 3.3 v or 2.5 v, r term = 100 between clk and clk# ??50mv v os [7] lvds offset output voltage v dd = 3.3 v or 2.5 v, r term = 100 between clk and clk# 1.125 ? 1.375 v v os change in v os between comple- mentary output states v dd = 3.3 v or 2.5 v, r term = 100 between clk and clk# ??50mv i oz output leakage current three-stat e output, unterminated, measured on one pin while floating the other pin, oe = v ss ?35 ? 35 a [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 3 of 9 v ih input high voltage, oe pin ? 0.7 v dd ??v v il input low voltage, oe pin ? ? ? 0.3 v dd v i ih input high current, oe pin oe = v dd ??115a i il input low current, oe pin oe = v ss ?50 ? ? a c in input capacitance, oe pin ? ? 15 ? pf c inx pin capacitance, xin & xout ? ? 4.5 ? pf dc electrical characteristics (continued) parameter description test conditions min typ max unit ac electrical characteristics [3] parameter description min typ max unit f out output frequency ? ? 100 ? mhz t r , t f [8] output rise or fall time 20% to 80% of full output swing ? 0.5 1.0 ns t jitter( ) [11] rms phase jitter (random) f out =100 mhz, (637 khz?10 mhz) ? 0.53 ? ps t dc [9] duty cycle measured at zero crossing point 45 ? 55 % t ohz [10] output disable time time from falling edge on oe to stopped outputs (asynchronous) ??100ns t oe [10] output enable time time from rising edge on oe to outputs at a valid frequency (asynchronous) ??120ns t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min.) ??5ms crystal characteristics parameter description min max unit mode of oscillation fundamental ? f frequency 25 25 mhz esr equivalent series resistance ? 50 c s shunt capacitance ?7pf notes 8. refer to figure 4 on page 4 . 9. refer to figure 5 on page 4 . 10. refer to figure 6 on page 4 . 11. refer to figure 7 on page 5 . [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 4 of 9 switching waveforms figure 2. output voltage swing figure 3. output offset voltage figure 4. output rise or fall time figure 5. duty cycle timing figure 6. output enable and disable timing clk clk# v od2 v od1 v od = v od1 - v od2 clk 50 clk# 50 v os 20% 80% t r clk 20% 80% clk# t f clk t pw t period t dc = t pw t period clk# oe clk high impedance t ohz t oe v il v ih clk# [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 5 of 9 figure 7. rms phase jitter termination circuits figure 8. lvds termination phase noise phase noise mark offset frequency f1 f2 rms jitter = area under the masked phase noise plot noise power clk clk# 100 [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 6 of 9 package drawing and dimensions figure 9. 8-pin thin shrunk small outline package (4.40 mm body) z8 ordering information part number package description product flow CY2XL11ZXC 8-pin tssop commercial, ?5 c to 70 c CY2XL11ZXCt 8-pin tssop - tape and reel commercial, ?5 c to 70 c cy2xl11zxi 8-pin tssop industrial cy2xl11zxi(t) 8-pin tssop - tape and reel industrial ordering code definitions t = tape and reel temperature range : c = commercial pb-free package type part identifier family company id: cy = cypress xx cy xxx z x t c 51-85093-*c [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 7 of 9 acronyms document conventions units of measures acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map eprom erasable programmab le read only memory lvds low-voltage differential signaling ntsc national televi sion system committee oe output enable pal phase alternate line pd power down pll phase locked loop ppm parts per million ttl transistor transistor logic symbol unit of measure c degrees celsius khz kilohertz k kilohms mhz megahertz m megaohms a microamperes s microseconds v microvolts vrms microvolts root-mean-square ma milliamperes mm millimeters ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ohms [+] feedback
cy2xl11 document number: 001-42886 rev. *f page 8 of 9 document history page document title: cy2xl11 100 mhz lvds clock generator document number: 001- 42886 rev. ecn no. submission date orig. of change description of change ** 2117527 see ecn wwz/kvm /aesa new data sheet *a 2669117 03/05/2009 kvm/ aesa changed crystal and output frequency removed msl spec changed iil value from -20 ua to -50 ua changed iih value from 20 ua to 115 ua changed phase jitter value from 1 to 0.53 ps changed junction temp from 125 c to 135 c changed idd from 150 ma to 120 ma rise / fall time changed to 350 ps to 500ps changed data sheet status to final *b 2700242 04/30/2009 kvm/ pyrs typo correction reformatted ac and dc tables added idd spec for 2.5v added cinx and tlock specs changed cin from 7pf to 15pf *c 2718433 06/12/2009 wwz/hmt no change. submit to ecn for product launch. *d 2764787 09/18/2009 kvm add clause to i oz test conditions change v od limits from 250/450 mv to 247/454 mv add max limit for t r , t f : 1.0 ns change t oe max from 100 ns to 120 ns change t lock max from 10 ms to 5 ms *e 3067416 10/20/20 bash added the industrial part in ordering information table. updated the package diagram. added ordering code definition, acronyms, and document conventions. *f 3199831 03/18/11 cxq no change. sunset review spec. [+] feedback
document number: 001-42886 rev. *f revised march 18, 2011 page 9 of 9 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2xl11 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
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